Method for exchanging information with physical layer component registers

ABSTRACT

A device and a method for exchanging information with registers of a physical layer component. The method includes allocating at least one receive buffer for receiving the status information; associating at least one receive buffer descriptor with the at least one receive buffer; sending to a physical layer component a request to read status information stored in a selected status register of the physical layer component; and writing the status information to the at least one receive buffer descriptor.

FIELD OF THE INVENTION

The invention relates to a method for exchanging information withphysical layer component registers and especially with status andcontrol registers of physical layer component and a device havingcontrol and status information exchanging capabilities.

BACKGROUND OF THE INVENTION

In today's communications, digital networks transport large amounts ofinformation. Network services can be, for example, traditional voicephone, facsimile, television, audio and video broadcast, and datatransfer.

Buffers and buffer descriptors are used to convey data. Buffers storedata to be transmitted or received while buffer descriptors point tothese buffers. Various examples of data transmission devices and methodsusing buffer descriptors are illustrated in the following U.S. patentsand patent applications, all being incorporated herein by reference:U.S. Pat. No. 6,212,593 of Pham et al., U.S. Pat. No. 6,735,210 ofLindeborg et al., U.S. Pat. No. 6,154,460 of Kerns et al., U.S. Pat. No.6,298,396 of Loyer et al., U.S. patent application 2004/0073724 ofWilson et al., U.S. patent application 2002/0176430 of Sangha et al.,U.S. patent application 2005/0243816 of Wrenn et al., U.S. patentapplication 2005/0093885 of Savekar et al., U.S. patent application2005/0068956 of Liao et al., and U.S. patent application 2002/0161943 ofKim.

Various communication protocols as well as various management protocolswere developed in order to support a variety of services andconfigurations.

The IEEE defined two management interface named MII management and GMIImanagement that use a two-wire serial interface to connect between amanagement entity and managed physical layer (PHY) components. GMII cansupport faster communication protocols than the MII. An exemplary devicethat includes such a serial interface is described in PCT patentapplication publication serial number WO 01/17166 of Kalapatapu which isincorporated herein by reference.

Each PHY component has multiple registers that can be accessed by usingthe MII management or GMII management interface. These registers can beaccessed in order to control the PHY components and gathering statusfrom the PHY components.

The management interface includes a pair of signals (clock andinformation signals), a management frame, a set of registers that can beread and written using the management frames, and a protocolspecification that defines the manner in which the management frame istransferred between the management entity and the PHY components. Thebasic (mandatory) set of registers of the MII management includes acontrol register and a status register. The MII management and the GMIImanagement use the same management frames and use the same signals. TheGMII management includes an additional basic register that is referredto as extended status register.

The control register is known as register 0. The status register isknown as register 1. The extended status register is known as register15. Registers 2-10 belong to an extended register set. This extendedregister set includes PHY identifier registers (registers 2 and 3),auto-negotiation advertisement register (register 4), auto-negotiationlink partner base page ability register (register 5), auto-negotiationexpansion register (register 6), auto-negotiation next page transmitregister (register 7), auto-negotiation link partner received next pageregister (register 8), MASTER-SLAVE control register (register 9) andMASTER-SLAVE status register (register 10).

FIG. 1 and FIG. 2 illustrates the content of control register 10, statusregister 30 and the extended status register 50.

Control register 10 includes the following fields: reserved (not used)field 11, speed selection fields (LSB and MSB) 12 and 19, collision testenable field 13, duplex mode field 14, restart auto-negotiation field15, isolate field 16, power down field 17, auto-negotiate enable field18, loopback field 20 and reset field 21. These fields control themanner in which the PHY component operates.

Status register 30 includes the following fields: extended capabilitiesfield 31, jabber detect field 32, link status field 33, auto-negotiationability field 34, remote fault field 35, auto-negotiation complete field36, MF preamble suppression field 37, reserved (not used) field 38,extended status field 39, 100BASE-T2 half duplex field 40, 100BASE-T2full duplex field 41, 10 Mb/s half duplex field 42, 10 Mb/s full duplexfield 43, 100BASE-X half duplex field 44 and 100BASE-T4 field 45.

Extended status register 50 includes the following fields: 1000BASE-Thalf duplex field 51, 1000BASE-T full duplex field 52, 1000BASE-X halfduplex field 53 and 1000BASE-X full duplex field 54. It also includesreserved bits (not shown).

Fields 31-54 indicate the status of the PHY component. For example, theyindicate the communication protocols it supports and the state of anauto-negotiation session conducted with that PHY component.

A single communication controller may be required to write controlinformation to physical layer component control registers and also toread status information from physical layer component status registers.One method for doing it involved polling the status register and controlregisters and determining whether data can be transferred, as well asusing dedicated registers within a register file to save parts of thestatus information or control information. Registers are more expensivethan simple memory unit entries. Accordingly, using registers wasresource consuming.

The polling method required a lot of processor intervention in order toknow when the access is done so valid data can be read.

FIG. 3 illustrates a management frame 80. Management frame 8C isserially transferred over a first line while a second line is used toconvey a clock signal. Multiple physical layer components are connectedin parallel to the information line and to the clock line.

The management frame 80 starts by a preamble field 81 (can be thirty twobits long) that is followed by a two bit long start of frame indication82 (value of ‘01’), a two bit long opcode 83 that indicate if the frameis being transferred during a read operation (from the register of thephysical layer component to the management entity) or a write operation,a five bit long physical layer component address 84, a five bit longregister address 85, a two bit long turnaround field 86, and a two-bytelong data field 87.

The complexity of status information and control information managementincreases as the number of physical layer registers increase.

There is a need to provide an efficient method and device for readingstatus information from status registers of physical layer components.

SUMMARY OF THE PRESENT INVENTION

A method for exchanging information with physical layer componentregisters and a device having control and status information exchangingcapabilities, as described in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 illustrates a prior art control register;

FIG. 2 illustrates a prior art status register and a prior art extendedstatus register;

FIG. 3 illustrates a prior art management frame;

FIG. 4 illustrates a communication device according to an embodiment ofthe invention;

FIG. 5 illustrates a communication engine according to an embodiment ofthe invention;

FIG. 6 illustrates an exemplary configuration of the communicationdevice, and its environment according to an embodiment of the invention;

FIG. 7 illustrates two serial peripheral interface registers accordingto an embodiment of the invention;

FIG. 8 illustrates exemplary data structures according to an embodimentof the invention;

FIG. 9 is a flow chart of a method according to an embodiment of theinvention; and

FIG. 10 is a flow chart of a method according to an embodiment of theinvention.

DETAILED DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention illustrated in the accompanyingdrawings provide a method. The method includes: allocating at least onereceive buffer for receiving the status information; associating atleast one receive buffer descriptor with the at least one receivebuffer; sending to a physical layer component a request to read statusinformation stored in a selected status register of the physical layercomponent; and writing the status information to the at least onereceive buffer descriptor.

Embodiments of the present invention illustrated in the accompanyingdrawings provide a device. The device includes a serial peripheralinterface that is adapted to send to a physical layer component arequest to read status information stored in a selected status registerof the physical layer component. The device is also adapted to: allocateat least one receive buffer for receiving the status information;associate at least one receive buffer descriptor with the at least onereceive buffer; write the status information to the at least one receivebuffer descriptor.

FIG. 4 illustrates a communication device 100, according to anembodiment of the invention.

Communication device 100 includes a first processor, such asgeneral-purpose processor 180, a security engine 170, system interfaceunit 140, communication engine 200 and multiple ports (not shown).Components 180, 170, 140 and 200 are connected to each other by centralbus 190.

The general-purpose processor 180 can include multiple execution unitssuch as but not limited to an integer unit, a branch processing unit, afloating point unit, a load/store unit and a system register unit. Itcan also include various cache memories, dynamic power management unit,translation look aside buffers, and the like.

The general-purpose processor 180 controls the communication device 100and can execute various programs according to the required functionalityof communication device 100. The general-purpose processor 180 can be amember of the PowerPC™ family but this is not necessarily so.

The security engine 170 can apply various security mechanisms includingencryption based mechanisms and the like.

Communication device 100 can be connected to multiple memory units aswell as other components. These components are interfaced by systeminterface unit 140. System interface unit 140 may include some of thefollowing components: external memory controllers 142, external DDRinterface unit 144, PCI bridge 146, local bus 148, bus arbitrator 150,Dual UART unit 152, dual 12C unit 154, a four channel DMA 156, interruptcontroller 158, protection and configuration unit 160, system reset unit162 and clock synthesizer 164. It is noted that other interfacingcomponents can be used.

FIG. 5 illustrates a communication engine 200, according to anembodiment of the invention.

It is noted that FIG. 5 illustrates an embodiment of the invention andthat other communication engines (including those who have a singleprocessor or more that two processors) can be used.

The communication engine 200 is a versatile communication component thatcan manage multiple communication ports that operate according todifferent communication protocols. It includes two RISC processors 220and 222 that can work substantially independently from each other.

The communication engine 200 includes two RISC processors 220 and 222,DMA controller 210, a shared data RAM memory unit 230, a sharedinstruction RAM memory unit 232, eight universal communicationcontrollers denoted UCC1-UCC8 241-248, one multi-channel communicationcontroller (MCC) 251, two serial peripheral interfaces denoted SPI1-SPI2252-253, two UTOPIA POS controllers 261 and 262, two time slot assigners264 and 266 and two communication interfaces 270 and 274. Time slotassigner 264 assigns time slots for accessing communication interface270. Time slot assigner 266 assigns time slots for accessingcommunication interface 274.

Each of the serial peripheral interfaces is adapted to managetransmissions and receptions of data, status information and controlinformation between the communication engine 200 and other components(such as PHY components) using serial communication protocols.

The first communication interface 270 is connected to multiple timedivision multiplex (TDM) ports that are collectively denoted 271, aUTOPIA-packet over SONET (POS) port 272, as well as four RMII portscollectively denoted 273, and four NMSI ports collectively denoted 274.

The second communication interface 274 is connected to anotherUTOPIA-packet over SONET (POS) port 275, four RMII ports collectivelydenoted 276, and four NMSI ports collectively denoted 274. It is notedthat other communication protocols can be supported by communicationdevice 100.

Each RISC processor out of 220 and 222 can access the shared data RAMmemory unit 230 and the shared instruction RAM memory unit 232. RISCprocessor 220 can control half of the multiple communication controllersand ports. For example, RISC processor 220 can control UCC1-UCC4241-244, MCC 251 and SPI1 252. It can also communicate with UTPOIA POScontroller 260 and time slot assigner 264.

Conveniently, a UCC can support the following communication protocolsand interfaces (not all simultaneously): 10/100 Mbps Ethernet, 1000 MpbsEthernet, ATM protocol via UTOPIA interface, various types of HDLC,UART, and BISYNC.

Conveniently, MCC 251 supports two hundred and fifty six HDLC ortransparent channels, one hundred and twenty eight SS#7 channels ormultiple channels that can be multiplexed to one or more TDM interfaces.

In addition, the communication engine 200 can include a controller (notshown) as well as an interrupt unit that coordinates the variouscomponents of the communication engine, as well as to enable thecommunication engine 200 to communicate with general-purpose processor110, security engine 62 and system interface unit 140.

The first RISC processor 220 is connected to a first hardwareaccelerator 223. The first hardware accelerator 223 can access theshared data RAM memory unit 230. The second RISC processor 222 isconnected to a second hardware accelerator 224.

The DMA controller 210 is connected to an external memory unit 212.

FIG. 6 illustrates an exemplary configuration of communication device100, and its environment, according to an embodiment of the invention.

Communication device 100 is illustrated as supporting a data path of aDSL line card 302. This DSL card 302, as well as many other DSL linecards can belong to a DSLAM.

Line card 302 also includes two DDR DRAM units 310 and 310, as well as aflash memory unit 330, all being connected to communication device 100via the system interface unit 140.

The communication engine 200 is configured as an xDSL line card and isconnected to multiple Ethernet PHY components 330 and 332, as well as toan ADSL PHY component 340. The communication device 100 supports ATMmulti-PHY subscriber lines and an Ethernet uplink.

FIG. 7 illustrates a serial peripheral interface (SPI1) 252, accordingto an embodiment of the invention. It is assumed that SPI2 is equivalentto SPI1 and that each serial peripheral interface operatedindependently.

SPI1 252 includes an SPI register file 430, a SPI controller 440, atransmit path (TX path) 450, a reception path (RX path) 460, a shiftregister 470 and a pins interface 480. It can access a parameter datastructure 540.

The SPI controller 440 executes commands and can perform various readand write operations, and especially capable of transmitting andreceiving data, control information and status information over seriallines such as MDC 482 and MDIO 482.

MDC 482 is a serial clock output signal. MDIO 482 is serial data line.

The SPI controller 440 is connected to the SPI register file 430, to TXpath 450 and to RX path 460. The shift register 470 is used to performserial to parallel conversions and parallel to serial conversions. It iscontrolled by the SPI controller 440. The shift register 470 isconnected to the TX path 450, to the RX path 460 and to the pinsinterface 480.

The TX path 450 and the RX path 460 can receive or transmit informationfrom/to the multiple bit bus that is connected to first RISC processor220. They can also send/get data to/from the shift register that in turnsends/gets the data in a serial manner via pins interface 480.

Conveniently, the SPI register file 430 is accessed by general purposeprocessor 180. It includes various registers such as SPI commandregister 420 and SPI mode register 400. The SPI command register 430includes reserved bits 422 and a start transmit instruction field 412.

The SPI mode register 400 includes the following fields: (i) Emergencyrequest (EM) field 401 that is used to indicate that an emergencyrequest should be sent to RISC 230, (ii) LOOP field 402 that indicatesif the SPI operates normally or whether the RX path and the TX path forma closed loop; (iii) Clock invert (CI) field 403 indicating what is theinactive state of MDC, (iv) Clock phase (CP) field 404 indicatingwhether the serial clock signals starts to toggle at the beginning orduring the middle of the data transfer, (v) DIV16 field 405 indicatingthe baud rate of the clock signal, (vi) data order (REV) field 406indicating whether the least significant bit or the most significantbits of data are received or transmitted first, (vi) Master/slave (M/S)field 407 that indicates if the SPI operates in slave more or in master(or MII) mode, (vii) Enable (EN) field 408 that indicates if the SPI isenabled, (viii) character length (LEN) field 409, (ix) clock pre-scaledivision (PM) field 410, (x) Operational mode (OP) field 411 indicatingif the SPI1 is controlled by the general purpose processor 180 or thefirst RISC processor 230, (xi) MII mode (MII) field 412 indicating ifthe SPI operates in MII mode or in normal (data) SPI mode, and (xii)Clock gap (CG) field 412 indicating the gap between two consecutivecharacters.

FIG. 8 illustrates various data structures 540-589, according to anembodiment of the invention.

The various data structures illustrated in FIG. 8 includes parameterdata structure 540 (stored in shared data RAM memory unit 230), areceive buffer descriptor table 550, a transmit buffer descriptor table560, multiple transmit buffers (collectively denoted 580) and multiplereceive buffers (collectively denoted 570).

Transmit buffers such as TX BUFFERs 581-589 can store data or controlinformation. At least one transmit buffer can be located in externalmemory units such as external memory unit 212 while at least one othertransmit buffer can be located in an internal memory unit such as shareddata RAM memory unit 230.

Receive buffers such as RX BUFFERs 571-579 can store data or statusinformation. At least one receive buffer can be located in externalmemory units such as external memory unit 212 while at least one otherreceive buffer can be located in an internal memory unit such as shareddata RAM memory unit 230.

Each receive buffer is associated with a receive buffer descriptor. RXBUFFERs 571-579 are associated with RX_BDs 551-559. Each transmit bufferis associated with a transmit buffer descriptor. TX BUFFERs 581-589 areassociated with TX_BDs 561-569.

Each receive buffer descriptor includes a frame status field, a datalength field and a buffer pointer. For example, RX_BD 551 includes aframe status field 551(1), data length field 551(2) and buffer pointerfield 551(3). Frame status field 551(1) indicates whether the buffer isfull, is BD_RX 551 the last buffer descriptor of table 550, whether togenerate an interrupt in response to the state of the buffer, whetherthe buffer contains the last character of a message, if the buffer hadoverrun and the like. Data length field 551(2) indicates the length ofreceived data. Buffer pointer field 551(3) stores a pointer to RX BUFFER571.

Each transmit buffer descriptor includes a frame status field, a datalength field and a buffer pointer. For example, TX_BD 569 includes aframe status field 569(1), data length field 569(2) and buffer pointerfield 569(3). Frame status field 569(1) indicates whether the buffer isready for transmitting, if TX_BD 569 the last buffer descriptor of table560, whether to generate an interrupt in response to the state of thebuffer, whether the buffer contains the last character of a message, ifthe buffer had underun and the like. Data length field 569(2) indicatesthe length of data to be transmitted from the buffer. Buffer pointerfield 569(3) stores a pointer to TX BUFFER 589.

The parameter data structure 540 includes multiple entries such as RBASE441, TBASE 442, RX BUS MODE 443, TX BUS MODE 444, MRBLR 445, RBPTR 446and TBPTR 447.

RBASE 441 is the base address of receive buffer descriptor table 550.TBASE 442 is the base address of transmit buffer descriptor table 560.RX BUS MODE 443 and TX BUS MODE 444 are bus mode register that storetransition specifications associated with DMA accesses to externalmemories such as memory unit 212. These accesses are conveniently madevia the bus that is also connected to the first RISC processor 230.

MRBLR 445 is the maximal receive buffer length. This value does notaffect the length of the transmit registers. RBPTR 446 points to thecurrent receive buffer descriptor (from table 550) that is being used orto the next receive buffer descriptor to be serviced when the SPI isidle. Its value can be initialized to RBASE (or indicate zero offsetfrom RBASE). It can be an offset from RBASE.

TBPTR 447 points to the current transmit buffer descriptor (from table560) that is being used or to the next transmit buffer descriptor to beserviced when the SPI is idle. Its value can be initialized to TBASE (orindicate zero offset from TBASE). It can be an offset from TBASE.

Up to thirty-two PHY components can be connected in parallel to MDC 481and MDIO 482. Each PHY component can include up to thirty-two registers.Thus, five bits are required to select between the PHY components andfive bits are required to select between the registers of the selectedPHY component.

The following example will further illustrate the various stages thatare executed when device 100 wishes to read status information from acertain status register of a certain PHY register. It is assumed thatthe status register is register 1, that the PHY component is the thirdPHY component connected to device 100, that RX BUFFER 571, RX_BD 551, TXBUFFER 581 and TX_BD 561 participate in the reception process, that theaddress of RX BUFFER 571 is 0x000_(—)1000, that the address of TX_BUFFER581 is 0x0000_(—)2008, and that two status bytes are read from thestatus register of the third PHY component.

When device 100 wishes to read the content of a certain status registerof a certain PHY component that is connected to SPI1 252 it performs thefollowing stages: (a) Configure pins interface 480 to enable MDC 481 andMDIO 482. (b) Write TBASE and RBASE to the parameter data structure 540.(c) Configure the bus mode registers, RX BUS MODE 443 and TX BUS MODE444. (d) Set MRBLR 445 to four bytes (size of MII management frame). (e)Initialize the frame status field 555(1), data length field 551(2) andset buffer pointer field 551 to point to 0x000_(—)1000. (f) Initializethe frame status field, data length field and set buffer pointer fieldof TX_BD 561. The buffer pointer field points to 0x000_(—)2008. (g)Write fields 81-85 of frame 80 to TX BUFFER 581. The preamble field 81is thirty bits long. The value of fields 82-85 can be: 01 (start offrame 82), 11(read operation, two-bit long opcode field 83), 00011(third PHY component, five bit PHY address field 85), 00001 (register 1,five bit register address field 85), and eighteen bits that areirrelevant (don't care) in fields 86 and 87. (h) writing a predefinedvalue to SPI mode register 400 such as to indicate that SPI1 252operates in a MII mode, operates as a master, sets the clock rate. (i)writing a start transmit command to SPI command register 420.

It is noted that some of the mentioned above stages are optional.

When these stages are executed the SPI will transmit the first portionof frame 80 to the physical layer devices, wait after the TA periodexpired and then receive the status information from register 1 of thethird PHY component and store it at RX BUFFER 571. The relevant statusinformation includes the last two bytes. TX buffer 581 is used totransmit the request to receive the status information.

The timing of the status read operation can be easily controlled bywriting the appropriate instructions to the SPI at the required timing.

FIG. 9 illustrates method 600 according to an embodiment of theinvention.

Method 600 starts by stage 610 of allocating at least one receive bufferfor receiving the status information. Referring to the example set forthin previous drawings, the number of allocated receive buffers isresponsive to the length of the received buffer and to the length ofdata that is supposed to be received. Typically, the buffers areimplemented in a memory units, thus they can be larger and even muchlarger than two bytes.

Stage 610 is followed by stage 620 of associating at least one receivebuffer descriptor with the at least one receive buffer. Thisconveniently includes setting a pointer from a buffer descriptor to acorresponding buffer. Typically, each buffer is associated with a singlebuffer descriptor.

Stage 620 is followed by stage 630 of allocating at least one transmitbuffer for transmitting the request. Referring to the example set forthin previous drawings the SPI transmits the beginning of the transmissionframe, thus the beginning of the frame can be stored in a transmitbuffer.

Stage 630 is followed by stage 640 of associating at least one transmitbuffer descriptor with the at least one transmit buffer. Thisconveniently includes setting a pointer from a buffer descriptor to acorresponding buffer.

Stage 640 is followed by stage 650 of defining a timing of the requestto read status information. The definition can be responsive to events,to a predefined status checking policy, and the like. By includingstatus read instructions that initiate the reading of status from thestatus registers within a code that is executed by either one of theRISC processors 230 and 232, the general purpose processor 180, or eventhe SPI 252 the timing of the read instruction can be easily defined.

Stage 650 is followed by stage 660 of fetching a status readinstruction. The fetching is part of the execution of the previouslymentioned code.

Stage 660 is followed by stage 670 of sending to a physical layercomponent a request to read status information stored in a selectedstatus register of the physical layer component. The request can beincluded within the beginning of a frame.

Stage 670 is followed by stage 680 of writing the status information tothe at least one receive buffer descriptor.

Method 600 can also includes stage 710 of allocating at least onereceive buffer for receiving the data. Stage 710 is followed by stage720 of associating at least one receive buffer descriptor with the atleast one receive buffer. Stage 720 is followed by stage 780 of writingthe data to the at least one receive buffer descriptor.

Conveniently, method 600 further includes stage 810 of writing controlinformation from a register within the management entity to controlinformation of the physical layer component.

It is noted that stages 710-780 as well as stage 810 can be executedbefore or after stages 610-680.

FIG. 10 is a flow chart of method 810, according to an embodiment of theinvention.

Method 810 can be executed as a part of method 600 or can be executedindependently from method 600.

Method 810 starts by stage 812 of associating at least one transmitbuffer descriptor with the at least one transmit buffer. Thisconveniently includes setting a pointer from a buffer descriptor to acorresponding buffer. Typically, each buffer is associated with a singlebuffer descriptor.

Stage 812 is followed by stage 813 of allocating at least one transmitbuffer for transmitting control information. Referring to the exampleset forth in previous drawings, the number of allocated transmit buffersis responsive to the length of the transmit buffer and to the length ofcontrol data that is going to be transmitted. Typically, the buffers areimplemented in a memory units, thus they can be larger and even muchlarger than two bytes.

Stage 813 is followed by stage 814 of defining a timing of thetransmission of control information. The definition can be responsive toevents, to a predefined status checking policy, and the like.

Stage 814 is followed by stage 815 of fetching a control writeinstruction. The fetching is part of the execution of the previouslymentioned code.

Stage 815 is followed by stage 816 of sending to a certain controlregister of a certain physical layer component control information,using the at least one transmit buffer.

Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

1. A method that comprises: sending to a physical layer component arequest to read status information stored in a selected status registerof the physical layer component; allocating at least one receive bufferfor receiving the status information; associating at least one receivebuffer descriptor with the at least one receive buffer; and writing thestatus information to the at least one receive buffer.
 2. The methodaccording to claim 1 further comprising: allocating at least onetransmit buffer for transmitting the request; associating at least onetransmit buffer descriptor with the at least one transmit buffer;wherein the sending comprises retrieving the request from the at leastone transmit buffer.
 3. The method according to claim 1 furthercomprising fetching a status read instruction and in response sending tothe physical layer component the request.
 4. The method according toclaim 3 wherein the fetching is preceded by defining a timing of therequest to read status information and fetching the status readinstruction in response to the timing.
 5. The method according to claim1 further comprising allocating at least one receive buffer forreceiving the data, associating at least one receive buffer descriptorwith the at least one receive buffer; writing the data to the at leastone receive buffer.
 6. The method according to claim 1 wherein thestatus information is IEEE 802.3 compliant.
 7. The method according toclaim 1 further comprising writing control information to a controlregister of a physical layer component.
 8. The method according to claim1 further comprising associating at least one buffer descriptor with atleast one transmit buffer that stores control information.
 9. The methodaccording to claim 1 further comprising sending to a certain controlregister of a certain physical layer component control information froma transmit buffer associated with a transmit buffer descriptor.
 10. Adevice comprising: a serial peripheral interface adapted to send to aphysical layer component a request to read status information stored ina selected status register of the physical layer component: wherein thedevice is adapted to allocate at least one receive buffer for receivingthe status information, associate at least one receive buffer descriptorwith the at least one receive buffer, and write the status informationto the at least one receive buffer.
 11. The device according to claim 10wherein the device is further adapted to allocate at least one transmitbuffer for transmitting the request; and associate at least one transmitbuffer descriptor with the at least one transmit buffer, wherein theserial peripheral interface is adapted to retrieve the request from theat least one transmit buffer.
 12. The device according to claim 10further adapted to fetch a status read instruction and in response sendto the physical layer component the request.
 13. The device according toclaim 12 wherein the device is further adapted fetch the status readinstruction at a predefined time.
 14. The device according to claim 10further adapted to allocate at least one receive buffer for receivingthe data, associate at least one receive buffer descriptor with the atleast one receive buffer, and write the data to the at least one receivebuffer.
 15. The device according to claim 10 wherein the statusinformation is IEEE 802.3 compliant.
 16. The device according to claim10 further adapted to write control information from a register withinthe serial peripheral interface to a control register of the physicallayer component.
 17. The device according to claim 10 further comprisingmultiple transmit buffers and wherein the device is adapted to transmitcontrol information to a certain control register of a certain physicallayer component, from a buffer associated with a buffer descriptor ofthe physical layer component.
 18. The method according to claim 2,further comprising fetching a status read instruction and in responsesending to the physical layer component the request.
 19. The methodaccording to claim 2, further comprising allocating at least one receivebuffer for receiving the data, associating at least one receive bufferdescriptor with the at least one receive buffer; writing the data to theat least one receive buffer.
 20. The method according to claim 2,further comprising writing control information to a control register ofa physical layer component.